Physical Design Engineer with 3+ years of experience in advanced-node semiconductor design (Intel 18A and Qualcomm 3nm/7nm), from floor planning to signoff. Currently pursuing a Master's in Technology & Design (IC Design, Failure Analysis & Reliability) at SUTD, where I have built a strong foundation in semiconductor device physics, IC design, failure analysis, and reliability engineering. During my internship at Wintech Nanotechnology Service Pte. Ltd., I gained practical exposure to package and die level failure analysis, electrical failure verification, fault localization, and advanced characterization techniques. My combined expertise in physical design and failure analysis enables me to contribute to improving semiconductor quality, yield, and product reliability.
SRI HARSHA CHEGERLA
Physical Design Engineer | Tech Mahindra (Cerium Systems)
Singapore
Summary
Education
'%3e%3crect%20width='48'%20height='48'%20rx='4'%20fill='%23E6E3F9'/%3e%3crect%20width='0.6'%20height='10'%20transform='matrix(-1%200%200%201%2042.3999%2024)'%20fill='%2367E2F2'/%3e%3cpath%20d='M44%2036C44%2037.1046%2043.1046%2038%2042%2038C40.8954%2038%2040%2037.1046%2040%2036C40%2034.8954%2040.8954%2034%2042%2034C43.1046%2034%2044%2034.8954%2044%2036Z'%20fill='url(%23paint0_linear_2586_8632)'/%3e%3cpath%20d='M42%2036L43.7321%2042H40.2679L42%2036Z'%20fill='url(%23paint1_linear_2586_8632)'/%3e%3crect%20x='-12'%20y='21.5'%20width='48'%20height='32'%20rx='2'%20fill='%236754C8'/%3e%3cpath%20d='M15.5493%2010.4661C16.1408%2010.1135%2016.8721%2010.0901%2017.485%2010.4041L41.5254%2022.72C42.9762%2023.4632%2042.9762%2025.5368%2041.5254%2026.28L17.485%2038.5959C16.8721%2038.9099%2016.1408%2038.8865%2015.5493%2038.5339L-5.11706%2026.2181C-6.41859%2025.4424%20-6.41859%2023.5576%20-5.11706%2022.7819L15.5493%2010.4661Z'%20fill='url(%23paint2_linear_2586_8632)'/%3e%3ccircle%20cx='31.9247'%20cy='24.1795'%20r='1.5'%20transform='rotate(-3.37875%2031.9247%2024.1795)'%20fill='white'/%3e%3ccircle%20cx='23.5357'%20cy='27.282'%20r='1.5'%20transform='rotate(-3.37875%2023.5357%2027.282)'%20fill='white'/%3e%3c/g%3e%3cdefs%3e%3clinearGradient%20id='paint0_linear_2586_8632'%20x1='38.0748'%20y1='42'%20x2='47.3606'%20y2='39.6343'%20gradientUnits='userSpaceOnUse'%3e%3cstop%20offset='0.0781'%20stop-color='%239685F4'/%3e%3cstop%20offset='1'%20stop-color='%2367E2F2'/%3e%3c/linearGradient%3e%3clinearGradient%20id='paint1_linear_2586_8632'%20x1='38.0748'%20y1='42'%20x2='47.3606'%20y2='39.6343'%20gradientUnits='userSpaceOnUse'%3e%3cstop%20offset='0.0781'%20stop-color='%239685F4'/%3e%3cstop%20offset='1'%20stop-color='%2367E2F2'/%3e%3c/linearGradient%3e%3clinearGradient%20id='paint2_linear_2586_8632'%20x1='-20.7546'%20y1='11.7454'%20x2='57.7546'%20y2='37.2546'%20gradientUnits='userSpaceOnUse'%3e%3cstop%20offset='0.0781'%20stop-color='%239685F4'/%3e%3cstop%20offset='1'%20stop-color='%2367E2F2'/%3e%3c/linearGradient%3e%3cclipPath%20id='clip0_2586_8632'%3e%3crect%20width='48'%20height='48'%20rx='4'%20fill='white'/%3e%3c/clipPath%3e%3c/defs%3e%3c/svg%3e)
Singapore University of Technology and Design (SUTD) M.Sc., Technology & Design (IC Design, Failure Analysis & Reliability) Aug 2026 - Present- Sree Vidyanikethan Engineering College (MBU) M.Tech., Electrical Power Systems Jan 2018 - Jan 2020
Experience
'%3e%3crect%20x='0.5'%20width='64'%20height='64'%20rx='8'%20fill='%23E6E3F9'/%3e%3cpath%20fill-rule='evenodd'%20clip-rule='evenodd'%20d='M44.4684%2011.2093C45.323%2011.7834%2045.8334%2012.7311%2045.8334%2013.7437V71.5903C45.8334%2073.2895%2044.4222%2074.667%2042.6813%2074.667H14.3188C12.578%2074.667%2011.1667%2073.2895%2011.1667%2071.5903V25.3228C11.1667%2024.0475%2011.9728%2022.9044%2013.1932%2022.449L41.5557%2010.8699C42.5247%2010.5083%2043.6139%2010.6352%2044.4684%2011.2093Z'%20fill='%236754C8'/%3e%3cpath%20fill-rule='evenodd'%20clip-rule='evenodd'%20d='M28.0802%2029.6378C28.6491%2029.2817%2029.364%2029.2345%2029.9764%2029.5127L55.3543%2041.0415C56.0531%2041.359%2056.5003%2042.0452%2056.5003%2042.8002V72.7279C56.5003%2073.7985%2055.6149%2074.6663%2054.5226%2074.6663H29.1447C28.0525%2074.6663%2027.167%2073.7985%2027.167%2072.7279V31.2715C27.167%2030.6099%2027.5113%2029.9939%2028.0802%2029.6378Z'%20fill='url(%23paint0_linear_2515_20613)'/%3e%3ccircle%20cx='45.9958'%20cy='45.5768'%20r='2.06863'%20transform='rotate(-3.92943%2045.9958%2045.5768)'%20fill='white'/%3e%3cellipse%20cx='34.7058'%20cy='42.2052'%20rx='2.06864'%20ry='2.06864'%20transform='rotate(-3.92943%2034.7058%2042.2052)'%20fill='white'/%3e%3c/g%3e%3cdefs%3e%3clinearGradient%20id='paint0_linear_2515_20613'%20x1='26.325'%20y1='65.8186'%20x2='57.9007'%20y2='59.5553'%20gradientUnits='userSpaceOnUse'%3e%3cstop%20offset='0.160358'%20stop-color='%239685F4'/%3e%3cstop%20offset='1'%20stop-color='%2367E2F2'/%3e%3c/linearGradient%3e%3cclipPath%20id='clip0_2515_20613'%3e%3crect%20x='0.5'%20width='64'%20height='64'%20rx='8'%20fill='white'/%3e%3c/clipPath%3e%3c/defs%3e%3c/svg%3e)
Physical Design Engineer Tech Mahindra (Cerium Systems) Apr 2024 - May 2025 • 1 yr 2 mos
Delivered Intel 1.8nm (18A) test-chip blocks end-to-end, from initial floorplan through final signoff. Constructed robust multi-supply PG grids and engineered voltage areas for secondary domains. Balanced clock skew across complex skew groups while resolving critical setup/hold violations
- Physical Design Engineer Digicomm Semiconductor Pvt. Ltd. May 2023 - Dec 2023 • 8 mos
Delivered a high-density Qualcomm 3nm block (1.5M instances, 4 macros) from floorplan to signoff. Optimised macro placement to mitigate severe routing congestion and drove full physical verification closure
Skills
- Physical DesignExpert
- Timing & ClosureExperienced
Languages
- EnglishNative speaker
- TeluguNative speaker